Bengaluru, Karnataka, India
Summary
As a Graduate Intern, led the design and implementation of a reusable TLM 2.0 interconnect model, significantly enhancing system modularity and efficiency for Intel's simulation infrastructure.
Highlights
Designed and implemented a reusable, configurable TLM 2.0 interconnect model in SystemC, incorporating advanced address normalization, remapping, and routing logic to optimize system performance.
Developed custom test benches and helper APIs for robust validation and dynamic configuration, ensuring high reliability and adaptability of the interconnect model.
Spearheaded the replacement of a legacy interconnect with the new TLM 2.0 model, reducing configuration code by over 50% and significantly improving modularity and maintainability across simulation infrastructure.
Automated build and regression flows using CMake and shell scripts, reducing debugging effort through GDB log analysis and enhanced trace logging, with changes validated via CI pipelines.